Variant X-Tree Clock Distribution Network and Its Performance Evaluations

Variant X-Tree Clock Distribution Network and Its Performance Evaluations

The evolution of VLSI chips towards larger die size, smaller feature size and faster clock speed makes the clock distribution an increasingly important issue. In this paper, we propose a new clock distribution network (CDN), namely Variant X-Tree, based on the idea of X-Architecture proposed recently for efficient wiring within VLSI chips. The Variant X-Tree CDN keeps the nice properties of equ...

Cview - A Salphasic Clock Distribution Tree Simulator

" " 5 4.066284e-03 " " 4.3 Other CVIEW modules \range" is used to prepare these output les for viewing on a Tektronix 4015 terminal or for plotting on a laser printer. It arranges scale factors and generates labels for the graphic output, providing more appropriate auto-scaling than is done by raw graph(1). This facility is automatically invoked by using any CVIEW command line display option. T...

Performance Evaluations in the Bali Atm-network

In 1993 the interconnection of three local ATM-based networks in Berlin was initiated by DeTeBerkom , the Gesellschaft für Mathematik und Datenverarbeitung (GMD) and the Technical University of Berlin (TUB). This paper describes the goals of this Berlin ATM LAN Interconnection (BALI) [Hartenthaler 94] and presents first results. Section 1 introduces the infrastructure of the BALI network in its...

High Performance Buffered X-architecture Zero-skew Clock Tree Construction with via Delay Consideration

As VLSI technology advances into nanometer dimensions, clock routing becomes a limiting factor in determining chip performance. To deal with the challenge, X-architecture has been proposed and widely applied in routing field because it contributes more improvements in terms of the clock delay, wirelength, and power consumption than general Manhattan-architecture. This work proposes an X-archite...

Clock Distribution Network Optimization under Self-Heating and Timing Constraints